The present invention relates to a digital timing recovery circuit of digital video equipment for recovering a sampling clock from an image playback signal, and more particularly, to a digital timing circuit for generating a stable sampling clock by means of varying the bandwidth of a loop filter.
In a conventional digital timing recovery circuit, the bandwidth of a loop filter is widened in order to curtail a phase obtaining time during the early stages of obtaining a sampling phase. Thus, the sampling phase changes greatly due to noise at a constant state, which causes a large phase error. In addition, upon hardware realization, a dead zone effect is produced by performing a quantization using a limited number of bits.
An accuracy of a bit clock extracted from a signal reproduced in a digital video equipment system affects on a general function of a reproducing system. Specifically, in a modern tendency for accomplishing a high density storing device, it is more important to precisely restore a bit clock since interference among recorded signals becomes serious. In general, a digital timing recovery circuit operates in a feedback structure, as follows. A phase error is detected from a sampled digital reproduction signal and a signal output via a digital filter is converted into an analog signal. Then, a variable voltage oscillator is adjusted and a reproduced signal is sampled with respect to the adjusted clock.
Every time a system skips when an initial operation is performed or in order to search a recorded program, there is a considerable difference between the phase of a sampling clock for sampling a reproduced signal and that of a bit clock of a reproduced signal. Therefore, a digital timing recovery circuit has to perform a phase obtaining operation. The phase obtaining operation mainly aims to record predetermined data and remove the difference between a sampling phase and a bit clock phase of a playback signal during a signal playback operation. Here, as the phase obtaining time becomes shorter, quantity of the required data can be reduced, thereby enhancing the recording density.
In general, a bit clock of a reproduced signal can be quickly traced by means of widening the bandwidth of a loop filter when a phase obtaining operation is performed in a digital timing recovery circuit. However, a phase error becomes large whenever phase obtaining is performed to an certain extent. Specifically, if a signal-to-noise ratio is low, a phase difference increases due to the noise, to thereby cause a great difference in a sampling clock. On the contrary, when the bandwidth of a loop filter becomes narrow in order to reduce a phase error, the sampling clock phase varies less at a state where a phase obtaining is completed to some extent. For this case, a problem exists in that a phase error obtaining time becomes longer.
Meanwhile, in consideration of hardware, data output from a loop filter has to be quantized to a limited number of bits so as to input the data to a digital-to-analog converter. However, the number of quantized bits has to accord with the number of bits required in the digital-to-analog converter. At this time, the number of the required bits is generally six to eight. Thus, quantization noise increases and a dead zone effect is produced. The dead zone effect is produced when a variable voltage oscillator control signal output from a loop filter is smaller than quantization step size .increment.. Here, a sampling phase control is no longer performed, despite a phase error detection. Since the quantization step size .increment. becomes larger as the number of quantization bits of the variable voltage oscillator control signal becomes smaller, a "dead zone" effect is enlarged.
The present invention is a digital timing recovery circuit that reduces a phase obtaining time, a phase error at a constant state and a dead zone effect caused by limiting a quantization of bits.